Product Descriptions

■ High-Performance Embedded  Architecture 

— 25 MIPS Burst Execution at 25 MHz

— 9.4 MIPS* Sustained Execution at  25 MHz 

■ 512-Byte On-Chip Instruction Cache 

— Direct Mapped 

— Parallel Load/Decode for Uncached  Instructions

■ Multiple Register Sets

— Sixteen Global 32-Bit Registers 

— Sixteen Local 32-Bit Registers

— Four Local Register Sets Stored  On-Chip

— Register Scoreboarding

■ 4 Gigabyte, Linear Address Space

■ Pin Compatible with 80960KA 

■ Built-in Interrupt Controller 

— 31 Priority Levels, 256 Vectors 

— 3.4 µs Latency @ 25 MHz

■ Easy to Use, High Bandwidth 32-Bit Bus 

 — 66.7 Mbytes/s Burst

— Up to 16 Bytes Transferred per Burst 

■ 132-Lead Packages: 

— Pin Grid Array (PGA) 

— Plastic Quad Flat-Pack (PQFP) 

 ■ On-Chip Floating Point Unit 

— Supports IEEE 754 Floating Point  Standard 

— Four 80-Bit Registers 

— 13.6 Million Whetstones/s (Single  Precision) at 25 MHz

Actual product photos

Product Data Manual:

For more product information, please download the PDF

Payment&Transportation

Official Certificate&Certificate

Multiple product supply

Company office environment

Warehouse Real Shot

Standard packaging

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