Product Descriptions

X2000/H is a low power consumption, high performance and high integrated application processor, the application is focus on AIoT devices. And it can match the requirements of many other embedded products.

Product Features

1.2.1 CPU Core

 XBurst®

2, at 1.2GHz, Dual Core, Dual-issue, high performance and low power implementation of MIPS32 ISA R5

 MIPS32 ISA R5 plus MIPS SIMD instruction set architecture:128bit MSA

 Ingenic SIMD instruction set architecture: 128bit MXA

 Dual-issue, superscalar, super pipeline with Simultaneous Multi-Threading (SMT)

– 2 hardware threads per physical core

– Quad instruction fetches per cycle

– Dual issue instructions per cycle per thread

 32KB L1 D cache +32K L1 I cache ，512 KB L2 cache，32KB SRAM

 High-performance Floating-point Unit and SIMD Engine: FSE

– 32 x 128-bit register set, 128-bit loads/stores to/from SIMD unit

– IEEE-754 2008 compliant

 Programmable Memory Management Unit (MMU)

– 1st level mini-TLBs (MTLBs) – 8 x 2 entry instruction TLB, 16 x 2 entry data TLB

– 2nd level TLBs: 32 × 2 entry VTLB, 256 × 2 entry 4-way set associative FTLB

 The XBurst® processor system supports little endian only 1.2.2 Video Process Unit(VPU)

 H.264 Encoder

– Input data format NV12/NV21

– Encoding resolution and frame rate up to 1920x1080@30fps

– Support hardware RBSP bytes insertion

– Support auto-read of slice header

– Support reference frame lossless compression

 H.264 Decoder

– Output data format NV12/NV21

– Decoding resolution and frame rate up to 1920x1080@30fps

– Support hardware RBSP bytes eliminate

 JPEG Codec

– JPEG compressing/decompressing up to 70Mega-pixels per second

– Baseline ISO/IEC 10918-1 JPEG compliant

– 8-bit pixel depth support

– Up to four programmable Quantization tables

– Fully programmable Huffman tables

Specifications

Actual product photos

Payment&Transportation

Official Certificate&Certificate

Multiple product supply

Company office environment

Warehouse Real Shot

Standard packaging

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