Product Details
| General Description The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each of the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. Features • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge, and auto refresh modes • Self refresh mode • 64ms, 8,192-cycle refresh • LVTTL-compatible inputs and outputs • Single +3.3V ±0.3V power supply |
Product Description
| Type | Description |
| ANSC PART# | ANSC- MT48LC16M16A2P-6A IT:G |
| PART# | MT48LC16M16A2P-6A IT:G |
| Category | Integrated Circuits (ICs) |
| Memory | |
| Memory | |
| Mfr | Original |
| Series | - |
| Packaging | Tray |
| Part Status | Last Time Buy |
| DigiKey Programmable | Not Verified |
| Memory Type | Volatile |
| Memory Format | DRAM |
| Technology | SDRAM |
| Memory Size | 256Mbit |
| Memory Organization | 16M x 16 |
| Memory Interface | Parallel |
| Clock Frequency | 167 MHz |
| Write Cycle Time - Word, Page | 12ns |
| Access Time | 5.4 ns |
| Voltage - Supply | 3V ~ 3.6V |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Mounting Type | Surface Mount |
| Package / Case | 54-TSOP (0.400", 10.16mm Width) |
| Supplier Device Package | 54-TSOP II |
| Base Product Number | MT48LC16M16A2 |
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