Product Details
General description The P89V51RB2/RC2/RD2 are 80C51 microcontrollers with 16/32/64 kB flash and 1024 B of data RAM. A key feature of the P89V51RB2/RC2/RD2 is its X2 mode option. The design engineer can choose to run the application with the conventional 80C51 clock rate (12 clocks per machine cycle) or select the X2 mode (six clocks per machine cycle) to achieve twice the throughput at the same clock frequency. Another way to benefit from this feature is to keep the same performance by reducing the clock frequency by half, thus dramatically reducing the EMI. The flash program memory supports both parallel programming and in serial ISP. Parallel programming mode offers gang-programming at high speed, reducing programming costs and time to market. ISP allows a device to be reprogrammed in the end product under software control. The capability to field/update the application firmware makes a wide range of applications possible. The P89V51RB2/RC2/RD2 is also capable of IAP, allowing the flash program memory to be reconfigured even while the application is running. Features - 80C51 CPU - 5 V operating voltage from 0 MHz to 40 MHz - 16/32/64 kB of on-chip flash user code memory with ISP and IAP - Supports 12-clock (default) or 6-clock mode selection via software or ISP - SPI and enhanced UART - PCA with PWM and capture/compare functions - Four 8-bit I/O ports with three high-current port 1 pins (16 mA each) - Three 16-bit timers/counters - Programmable watchdog timer - Eight interrupt sources with four priority levels - Second DPTR register - Low EMI mode (ALE inhibit) - TTL- and CMOS-compatible logic levels - Brownout detection - Low power modes - Power-down mode with external interrupt wake-up - Idle mode - DIP40, PLCC44 and TQFP44 packages |
Product Description
| Type# | Description |
| ANSC PART# | ANSC - P89V51RB2FN |
| Part Package Code | DIP |
| Package Description | Dip, Dip40,.6 |
| Pin Count | 40 |
| Reach Compliance Code | Unknown |
| Has ADC | No |
| Address Bus Width | 16 |
| Bit Size | 8 |
| Boundary Scan | Yes |
| CPU Family | 8051 |
| Clock Frequency-Max | 40 Mhz |
| DAC Channels | No |
| DMA Channels | No |
| External Data Bus Width | 8 |
| JESD-30 Code | R-PDIP-T40 |
| Length | 52 Mm |
| Number of I/O Lines | 32 |
| Number of Terminals | 40 |
| On Chip Program ROM Width | 8 |
| Operating Temperature-Max | 85 °C |
| Operating Temperature-Min | -40 °C |
| PWM Channels | Yes |
| Package Body Material | Plastic/Epoxy |
| Package Code | DIP |
| Package Equivalence Code | DIP40,.6 |
| Package Shape | Rectangular |
| Package Style | In-Line |
| Peak Reflow Temperature (Cel) | 245 |
| Qualification Status | Not Qualified |
| RAM (bytes) | 1024 |
| ROM (words) | 16384 |
| ROM Programmability | Flash |
| Seated Height-Max | 4.7 Mm |
| Speed | 40 Mhz |
| Supply Current-Max | 50 Ma |
| Supply Voltage-Max | 5.5 V |
| Supply Voltage-Min | 5 V |
| Supply Voltage-Nom | 5 V |
| Surface Mount | No |
| Technology | Cmos |
| Temperature Grade | Industrial |
| Terminal Form | Through-Hole |
| Terminal Pitch | 2.54 Mm |
| Terminal Position | Dual |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Width | 7.62 Mm |
| uPs/uCs/Peripheral ICs Type | Microcontroller |
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