Product Descriptions
This section describes a high-level overview including features and general operation of the MPC8360E/58E PowerQUICC II Pro processor. A major component of this device is the e300 core, which includes 32 Kbytes of instruction and data cache and is fully compatible with the Power Architecture™ 603e instruction set. The new QUICC Engine module provides termination, interworking, and switching between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine module’s enhanced interworking eases the transition and reduces investment costs from ATM to IP based systems. The other major features include a dual DDR SDRAM memory controller for the MPC8360E, which allows equipment providers to partition system parameters and data in an extremely efficient way, such as using one 32-bit DDR memory controller for control plane processing and the other for data plane processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine.
Product Specifications
| Attribute | Attribute value |
| ANSM-Part# | ANSM-MPC8358EZQAGDDA |
| Category | Integrated Circuits (ICs) |
| Embedded | |
| Microprocessors | |
| Manufacturer | - |
| Series | MPC83xx |
| Packaging | Bulk |
| Part Status | Active |
| Core Processor | PowerPC e300 |
| Number of Cores/Bus Width | 1 Core, 32-Bit |
| Speed | 400MHz |
| Co-Processors/DSP | Communications; QUICC Engine, Security; SEC |
| RAM Controllers | DDR, DDR2 |
| Graphics Acceleration | No |
| Display & Interface Controllers | - |
| Ethernet | 10/100/1000Mbps (1) |
| SATA | - |
| USB | USB 1.x (1) |
| Voltage - I/O | 1.8V, 2.5V, 3.3V |
| Operating Temperature | 0°C ~ 105°C (TA) |
| Security Features | Cryptography, Random Number Generator |
| Mounting Type | Surface Mount |
| Package / Case | 668-BBGA Exposed Pad |
| Supplier Device Package | 668-TEPBGA (29x29) |
| Additional Interfaces | DUART, HDLC, I2C, PCI, SPI, UART |
Product Photos
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