Product Functions

• ITU I.363.5 AAL5 SAR

• OC-12 throughput

• 32K bi-directional connections

• Traffic shaping - dual GCRA per connection

• Supports the following traffic shaping conformance definitions:

- CBR.1

- VBR.1

- UBR.1

- UBR.2

• VP tunnels with WRR access

• VC tunnels with WFQ access

• Congestion control:

- Weighted random early detection (WRED)

- Per VC flow control

- Per VC early packet discard (EPD)

• Reassembly time-out

• Encapsulation/De-encapsulation

• Support for raw cells (AAL0)

• Host control via PCI bus

• Per connection and per port statistics

- Bytes transmitted/received

- Packets transmitted/received

- Packets discarded due to resource exhaustion

- Packets discarded due to error conditions

• Memory requirements:

– 16 to 256 Mbytes of SDRAM

– 4 Mbytes of SRAM

See the CX27470 data sheet for a description of the hardware interfaces and device characteristics.

Ordering Information

• Binary: MXA-pm2a5-bn

• Source: MXA-pm2a5-sc

Product Features

> Bi-directional OC-12 throughput

>∑ITU I.363.5 compliant AAL5 SAR

> ATM Forum TM 4.1 traffic shaping

> Per VC queuing

> Choice of segmenter queue admission policies:

- Weighted random early detection (WRED),

- Per VC flow control

- Per VC early packet discard (EPD)

> VP and VC tunnels

> Encapsulation/ De-encapsulation

> Reassembly time-out

> Support for raw cells (AAL0)

> Per PHY and per connection statistics

> Host control via PCI bus and software API

> Traffic shaping rates configurable from 0.006 percent to 100 percent of line rate, with 1 percent accuracy

> Supports 32K bi-directional connections

Product Photos

For more product information, please download the PDF