Product Descriptions
The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks is organized as 4096 rows by 2048 columns by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4096 rows by 1024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4096 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[11:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
Product Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive edge of system clock
• Internal, pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths (BL): 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge and auto refresh modes
• Self refresh modes: Standard and low power (not available on AT devices)
• Auto Refresh
– 64ms, 4096-cycle refresh (commercial and industrial)
– 16ms, 4096-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
Product Specification
| Attribute | Attribute value |
| ANSM-Part# | ANSM-MT48LC16M8A2BB-75 IT:G |
| Category | Integrated Circuits (ICs) |
| Memory | |
| Memory | |
| Mfr | - |
| Packaging | Tray |
| Part Status | Obsolete |
| DigiKey Programmable | Not Verified |
| Memory Type | Volatile |
| Memory Format | DRAM |
| Technology | SDRAM |
| Memory Size | 128Mbit |
| Memory Organization | 16M x 8 |
| Memory Interface | Parallel |
| Clock Frequency | 133 MHz |
| Write Cycle Time - Word, Page | 15ns |
| Access Time | 5.4 ns |
| Voltage - Supply | 3V ~ 3.6V |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Mounting Type | Surface Mount |
| Package / Case | 60-FBGA |
| Supplier Device Package | 60-FBGA (8x16) |
| Base Product Number | MT48LC16M8A2 |
Product Photos
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